Agreed capacitive crosstalk can be higher, but you can shield that out. What I was referring to was Johnson noise changing the switching point of the gate at high frequencies. When the first CMOS devices appeared we were regularly seeing this creating logic errors because there is a point where neither MOS transistor is on and the impedance went extremely high for a moment - flip-flops built with gates often didn't work unless you added a capacitor.That's the law for Johnson (thermal) voltage noise, in digital systems its capacitive crosstalk that is the problem (many orders of magnitude above thermal noise), and susceptibility to that goes up linearly with impedance - but just how much cross talk capacitance there is controls what impedance level is immune - in very noisy environments strong pull-ups like 1k might be needed, in other situations 100k may be adequate. Any signal that leaves the PCB will be much more susceptible to noise and on-chip pull-ups are usually too weedy to deal with that.
10k isn't that low impedance. High impedance inputs are subject to noise which rises with the square root of the impedance.
But running a CMOS input over some distance without any load resistance is still a bad idea no matter what noise source you wish to consider is greater.
Statistics: Posted by MikeDB — Tue Sep 03, 2024 8:49 pm
