I don't think there's been evidence shown of sinking current as well as sourcing it. That element14 forum post linked above uses the words "The IO pad is sourcing and sinking current" but the accompanying scope shot doesn't show that - it only shows the pin sourcing current: comparing the problem scope shot with the pin loading against the one with input disabled (that just shows a sinewave), the voltage in the problem case is always above or equal to the equivalent point on the sinewave, so only sourcing, never sinking (which would give a voltage below the sinewave). There are points on the plot where the voltage suddenly drops, but this isn't the pin sinking current, it's the pin ceasing to source current and reverting to normal.I suppose I2C would be affected too if the pin is now sinking current in addition to sourcing it? With a pull resistor on the low end of what's allowed it'll probably work ok.
So it appears that I2C is pretty much unaffected, with the extra source current due to the erratum simply adding to the effect of the pull-up resistor (and being quite small in comparison to sensible values of I2C pull-up).
One think I haven't seen reported yet is the behaviour with the on-chip pull-up enabled: is the erratum not applicable in that case, or does it source a little bit of extra current in addition to the pull-up? It matters much less than the other cases (because the the pull-up already has a wide tolerance), but would be interesting to know.
Statistics: Posted by arg001 — Wed Sep 04, 2024 8:10 pm
