Yes, but my confusion was with what is effectively a 16 bit array for the DMA, addressed in 8 bit chunks. I was thinking that byte 0 was or should have been the MSB of the 16 bit word, but really it is the LSB of the 16 bit word.We tend to humanly read left to right so a 16 bit word would be low order on the right, high order on the left but we read left to right so I somehow was visualizing the byte map as 0, 1, 2, 3, 4, etc. But since the CPU is reading right to left, the byte order is actually 4, 3, 2, 1, 0
So it is correct to have the low order bits of the 16 bit word in byte 0, and high order bits in byte 1.
I find the same, the WS2812B spec shows bit order left to right, after you have flung the data through various other hardware/software, keeping track of bit order, byte order and word order is very confusing, I ended up doing it empirically, far quicker and no uncertainty.
Statistics: Posted by DanMan32 — Sun Jan 14, 2024 3:32 am
