Barriers, Atomic and the multiple processing way:
Barriers are control flow instructions within a single core. Atomic is external to a single core. SMT technically is external like CMT. The performance of NUMA is tempting till you start writing device drivers. Then you have to peg the memory controller using an uncached region. At this point you can implement a lockless algorithm successfully. Intel however disagreed with this.
Atomic on coherent:
Atomic is supposed to invalidate. The memory values are the control flow. ARM does support coherent on some of their UMA network designs. Variable scalar and variable memory controller design should still be supported. The prediction of this is Apple does not use a L3 coherent network in multi-controller. You can optimize the size of L3 cache per domain and still get the feedback required for NUMA to pretend to be UMA. It has to trickle back to the highest domain. ARM has no support? A CMT capable OS just makes more sense to me.
Everytime you want a lock you must:
Caches:
If they use eviction write caches then you need to explicitly flush the cache. Write through caches usually self invalidate on coherent buses. I would blame the compiler and/or OS for not issuing the correct procedure. These caches are significantly faster on high thread systems I would imagine. They work on the idea of copy checkout and commit write. These are compute caches not IO caches. C++ likely assumes IO caches or coherency on multitasking.
You never touch RAM, but you do stall multiple domains. Naturally you would never parallelize high commit threads. High commit threads would be scheduled onto the same memory controller. You would use copy checkout procedure.
Barriers are control flow instructions within a single core. Atomic is external to a single core. SMT technically is external like CMT. The performance of NUMA is tempting till you start writing device drivers. Then you have to peg the memory controller using an uncached region. At this point you can implement a lockless algorithm successfully. Intel however disagreed with this.
Atomic on coherent:
Atomic is supposed to invalidate. The memory values are the control flow. ARM does support coherent on some of their UMA network designs. Variable scalar and variable memory controller design should still be supported. The prediction of this is Apple does not use a L3 coherent network in multi-controller. You can optimize the size of L3 cache per domain and still get the feedback required for NUMA to pretend to be UMA. It has to trickle back to the highest domain. ARM has no support? A CMT capable OS just makes more sense to me.
Everytime you want a lock you must:
- Lock the L3 line
- Invalidate all L1 and L2 caches
- Write to L3
- Release the L3 line
Caches:
If they use eviction write caches then you need to explicitly flush the cache. Write through caches usually self invalidate on coherent buses. I would blame the compiler and/or OS for not issuing the correct procedure. These caches are significantly faster on high thread systems I would imagine. They work on the idea of copy checkout and commit write. These are compute caches not IO caches. C++ likely assumes IO caches or coherency on multitasking.
You never touch RAM, but you do stall multiple domains. Naturally you would never parallelize high commit threads. High commit threads would be scheduled onto the same memory controller. You would use copy checkout procedure.
Statistics: Posted by dthacher — Fri Dec 06, 2024 4:17 pm