RP1 being the I/O controller used on RPI 5, right ?When trying something vaguely similar on RP1 I observed a total round trip delay (pin1 -> PIO (wait gpio; side set) -> pin2) of about 30 ns or 6 cycles.
Actually, when playing at 100-400 MHz clock with RP2350, I've been able to see the analog delay on the PIN (comparable and detectable at 2.5 ns clock period), with and without synchronizers (got metastable state for a shot time, as well), also Schmidt trigger and drive strength influence. It really goes all the way around (like a proper loop-back):
SM Out map> PIO Out mux -> GPIO Out mux -> PAD Output -> PIN -> PAD Input -> (GPIO In mux + PIO sync) -> PIO In -> SM In map
(and I think the picture is not complete, it doesn't show how each PIO blocks are combined)
Statistics: Posted by gmx — Mon Dec 23, 2024 7:51 pm