I can't comment on what Xilinx might get up to.
The link frequency control (V4L2_CID_LINK_FREQ) gives the frequency of the clock lane in MHz.
CSI2 is DDR (Double Data Rate) so clocks a bit of data on each clock edge.
A LINK_FREQ of 500MHz therefore allows 1 data lane to transfer 1000Mbit/s of data. Multiply by the number of lanes as they'll all transfer data simultaneously.
The link frequency control (V4L2_CID_LINK_FREQ) gives the frequency of the clock lane in MHz.
CSI2 is DDR (Double Data Rate) so clocks a bit of data on each clock edge.
A LINK_FREQ of 500MHz therefore allows 1 data lane to transfer 1000Mbit/s of data. Multiply by the number of lanes as they'll all transfer data simultaneously.
Statistics: Posted by 6by9 — Thu Mar 07, 2024 3:06 pm