Note that uart_set_irq_enables() enables the rx timeout interrupt as well as the rx interrupt.
Is it possible that there's a delay (>32 bit times) after the first byte, and the timeout is firing?
(Also, it seems odd to configure the FIFO after enabling everything.)
Is it possible that there's a delay (>32 bit times) after the first byte, and the timeout is firing?
(Also, it seems odd to configure the FIFO after enabling everything.)
Statistics: Posted by jeremyd — Thu Aug 15, 2024 5:36 pm
